`include "defines.svh"
module HILO (
    input logic clk,
    input logic reset,
    input logic EXE_Finish,
    input logic HiLo_Not_Flush,
    input logic [31:0]EXE_DatatoHI,
    input logic [31:0]EXE_DatatoLO,
    input logic [31:0]Data_In,//EXE_Rs_Data
    input logic [2:0]EXE_Reg_Writed,


    output logic [31:0]HI_Data,
    output logic [31:0]LO_Data

);
    logic [31:0]HI;
    logic [31:0]LO;

    always_comb begin
        if(EXE_Finish&&HiLo_Not_Flush)begin
            HI_Data = EXE_DatatoHI;
        end
        else if(EXE_Reg_Writed == `RegWrited_HI && HiLo_Not_Flush)begin
            HI_Data = Data_In;
        end
        else 
            HI_Data = HI;
    end

    always_comb begin
        if(EXE_Finish&&HiLo_Not_Flush)begin
            LO_Data = EXE_DatatoLO;
        end
        else if(EXE_Reg_Writed == `RegWrited_LO &&HiLo_Not_Flush)begin
            LO_Data = Data_In;
        end
        else 
            LO_Data = LO;
    end

    always @(posedge clk,negedge reset) begin
        if(!reset)
            HI <= 32'b0;
        else if(EXE_Finish&&HiLo_Not_Flush)
            HI <= EXE_DatatoHI;
        else if(EXE_Reg_Writed == `RegWrited_HI && HiLo_Not_Flush)
            HI <= Data_In;
    end

    always @(posedge clk,negedge reset) begin
        if(!reset)
            LO <= 32'b0;
        else if(EXE_Finish&&HiLo_Not_Flush)
            LO <= EXE_DatatoLO;
        else if(EXE_Reg_Writed == `RegWrited_LO && HiLo_Not_Flush)
            LO <= Data_In;
    end
endmodule